-- Catapult University Version: Report                                              
-- ---------------------------- ---------------------------------------------------
-- Version:                     2010a.198 Production Release                        
-- Build Date:                  Tue Nov  2 16:54:20 PDT 2010                        
                                                                                    
-- Generated by:                joaopizani@pilsener                                 
-- Generated date:              Tue Mar 29 16:47:07 BRT 2011                        

Solution Settings: mult_acc.v1
  Current state: schedule
  Project: Catapult
  
  Design Input Files Specified
    $PROJECT_HOME/mac_tb.cpp
      $MGC_HOME/shared/include/mc_scverify.h
    $PROJECT_HOME/mac.cpp
  
  Processes/Blocks in Design
    Process        Real Operation(s) count Latency Throughput Reset Length II Comments 
    -------------- ----------------------- ------- ---------- ------------ -- --------
    /mult_acc/core                       8       4          6            0  0          
    Design Total:                        8       4          6            0  0          
    
  Clock Information
    Clock Signal Edge   Period Sharing Alloc (%) Used by Processes/Blocks 
    ------------ ------ ------ ----------------- ------------------------
    clk          rising  3.003             20.00 /mult_acc/core           
    
  I/O Data Ranges
    Port       Mode DeclType DeclWidth DeclRange ActType ActWidth ActRange 
    ---------- ---- -------- --------- --------- ------- -------- --------
    a:rsc.z    IN   Unsigned       128                                     
    b:rsc.z    IN   Unsigned       128                                     
    clk        IN   Unsigned         1                                     
    rst        IN   Unsigned         1                                     
    dout:rsc.z OUT  Unsigned        32                                     
    
  Memory Resources
    Resource Name: /mult_acc/a:rsc
      Memory Component: mgc_in_wire                  Size:         1 x 128
      External:         true                         Packing Mode: sidebyside
      Memory Map:
      Variable    Indices Phys Memory Address     
      ----------- ------- -----------------------
      /mult_acc/a   0:127 00000000-00000000 (0-0) 
      
    Resource Name: /mult_acc/b:rsc
      Memory Component: mgc_in_wire                  Size:         1 x 128
      External:         true                         Packing Mode: sidebyside
      Memory Map:
      Variable    Indices Phys Memory Address     
      ----------- ------- -----------------------
      /mult_acc/b   0:127 00000000-00000000 (0-0) 
      
    Resource Name: /mult_acc/dout:rsc
      Memory Component: mgc_out_stdreg               Size:         1 x 32
      External:         true                         Packing Mode: sidebyside
      Memory Map:
      Variable       Indices Phys Memory Address     
      -------------- ------- -----------------------
      /mult_acc/dout    0:31 00000000-00000000 (0-0) 
      
  Multi-Cycle (Combinational) Component Usage
    Instance Component Name Delay 
    -------- -------------- -----
    
  Loops
    Process        Loop             Iterations C-Steps Total Cycles  Duration  Unroll Init Comments 
    -------------- ---------------- ---------- ------- ------------- --------- ------ ---- --------
    /mult_acc/core main               Infinite       2            6  18.02 ns                       
    /mult_acc/core   MAC                     4       1            4  12.01 ns                       
    
  Loop Execution Profile
    Process        Loop             Total Cycles % of Overall Design Cycles Throughput Cycles Comments 
    -------------- ---------------- ------------ -------------------------- ----------------- --------
    /mult_acc/core main                       2                       33.33                6           
    /mult_acc/core   MAC                      4                       66.67                4           
    
  End of Report
