-- Catapult University Version: Report                                              
-- ---------------------------- ---------------------------------------------------
-- Version:                     2010a.198 Production Release                        
-- Build Date:                  Tue Nov  2 16:54:20 PDT 2010                        
                                                                                    
-- Generated by:                joaopizani@pilsener                                 
-- Generated date:              Tue Mar 29 16:47:10 BRT 2011                        

Solution Settings: mult_acc.v1
  Current state: extract
  Project: Catapult
  
  Design Input Files Specified
    $PROJECT_HOME/mac_tb.cpp
      $MGC_HOME/shared/include/mc_scverify.h
    $PROJECT_HOME/mac.cpp
  
  Processes/Blocks in Design
    Process        Real Operation(s) count Latency Throughput Reset Length II Comments 
    -------------- ----------------------- ------- ---------- ------------ -- --------
    /mult_acc/core                       8       4          6            0  0          
    Design Total:                        8       4          6            0  0          
    
  Bill Of Materials (Datapath)
    Component Name                    Area Score Delay Post Alloc Post Assign 
    --------------------------------- ---------- ----- ---------- -----------
    [Lib: mgc_ioport]                                                         
    mgc_in_wire(1,128)                     0.000 0.000          1           1 
    mgc_in_wire(2,128)                     0.000 0.000          1           1 
    mgc_out_stdreg(3,32)                   0.000 0.000          1           1 
    [Lib: mgc_sample-065nm-dw_beh_dc]                                         
    mgc_add(2,0,2,1,3,4)                  18.755 0.199          1           1 
    mgc_add(32,0,32,0,32,2)              494.875 0.509          1           1 
    mgc_and(2,2,4)                         4.800 0.030          0           1 
    mgc_and(32,2,4)                       76.800 0.030          0           1 
    mgc_mul(32,0,32,0,32,3)             4710.423 1.419          1           1 
    mgc_mux(32,1,2,3)                    127.903 0.081          0           1 
    mgc_mux(32,2,4,1)                    509.211 0.084          2           2 
    mgc_nand(1,2,1)                        4.000 0.007          0           1 
    mgc_reg_pos(2,0,0,1,1,0,0,2)          39.731 0.121          0           1 
    mgc_reg_pos(32,0,0,1,1,0,0,2)        635.688 0.121          0           2 
                                                                              
    TOTAL AREA (After Assignment):      7767.085                              
    
  Area Scores
                      Post-Scheduling   Post-DP & FSM Post-Assignment 
    ----------------- --------------- --------------- ---------------
    Total Area Score:   7513.9          7840.3          7795.1        
    Total Reg:          1271.4  (17%)   1335.1  (17%)   1335.1  (17%) 
                                                                      
    DataPath:           7513.9 (100%)   7812.3 (100%)   7767.1 (100%) 
      MUX:              1018.4  (14%)   1185.9  (15%)   1146.3  (15%) 
      FUNC:             5224.1  (70%)   5224.1  (67%)   5224.1  (67%) 
      LOGIC:               0.0            91.2   (1%)     85.6   (1%) 
      BUFFER:              0.0             0.0             0.0        
      MEM:                 0.0             0.0             0.0        
      ROM:                 0.0             0.0             0.0        
      REG:              1271.4  (17%)   1311.1  (17%)   1311.1  (17%) 
                                                                      
    
    FSM:                   0.0            28.0   (0%)     28.0   (0%) 
      FSM-REG:             0.0            24.0  (86%)     24.0  (86%) 
      FSM-COMB:            0.0             4.0  (14%)      4.0  (14%) 
                                                                      
    
  Register-to-Variable Mappings
    Register                  Size(bits) Gated Register CG Opt Done Variables                                             
    ------------------------- ---------- -------------- ----------- -----------------------------------------------------
    MAC:i#1.sva#2                      2                            MAC:i#1.sva#2                                         
    acc.sva                           32                            acc.sva                                               
    dout:rsc:mgc_out_stdreg.d         32                            dout:rsc:mgc_out_stdreg.d                             
                                                                                                                          
    Total:                            66              0           0 (Total Gating Ratio: 0.00, CG Opt Gating Ratio: 0.00) 
    
  Timing Report
    Critical Path
      Max Delay:  2.21481502
      Slack:      0.78818798
      
      Path                                           Startpoint                        Endpoint                                     Delay  Slack  
      ---------------------------------------------- --------------------------------- -------------------------------------------- ------ ------
      1                                              mult_acc:core/reg(MAC:i#1.sva#2)  mult_acc:core/reg(dout:rsc:mgc_out_stdreg.d) 2.2148 0.7882 
                                                                                                                                                  
        Instance                                     Component                                                                      Delta  Delay  
        --------                                     ---------                                                                      -----  -----  
        mult_acc:core/reg(MAC:i#1.sva#2)             mgc_reg_pos_2_0_0_1_1_0_0_2                                                    0.1207 0.1207 
        mult_acc:core/MAC:i#1.sva#2                                                                                                 0.0000 0.1207 
        mult_acc:core/MAC:mux                        mgc_mux_32_2_4_1                                                               0.0843 0.2051 
        mult_acc:core/MAC:mux.itm                                                                                                   0.0000 0.2051 
        mult_acc:core/MAC:mul                        mgc_mul_32_0_32_0_32_3                                                         1.4191 1.6241 
        mult_acc:core/MAC:mul.itm                                                                                                   0.0000 1.6241 
        mult_acc:core/MAC:acc#3                      mgc_add_32_0_32_0_32_2                                                         0.5094 2.1336 
        mult_acc:core/acc.sva#1                                                                                                     0.0000 2.1336 
        mult_acc:core/mux#2                          mgc_mux_32_1_2_3                                                               0.0812 2.2148 
        mult_acc:core/mux#2.itm                                                                                                     0.0000 2.2148 
        mult_acc:core/reg(dout:rsc:mgc_out_stdreg.d) mgc_reg_pos_32_0_0_1_1_0_0_2                                                   0.0000 2.2148 
                                                                                                                                                  
      2                                              mult_acc:core/reg(MAC:i#1.sva#2)  mult_acc:core/reg(dout:rsc:mgc_out_stdreg.d) 2.2148 0.7882 
                                                                                                                                                  
        Instance                                     Component                                                                      Delta  Delay  
        --------                                     ---------                                                                      -----  -----  
        mult_acc:core/reg(MAC:i#1.sva#2)             mgc_reg_pos_2_0_0_1_1_0_0_2                                                    0.1207 0.1207 
        mult_acc:core/MAC:i#1.sva#2                                                                                                 0.0000 0.1207 
        mult_acc:core/MAC:mux#1                      mgc_mux_32_2_4_1                                                               0.0843 0.2051 
        mult_acc:core/MAC:mux#1.itm                                                                                                 0.0000 0.2051 
        mult_acc:core/MAC:mul                        mgc_mul_32_0_32_0_32_3                                                         1.4191 1.6241 
        mult_acc:core/MAC:mul.itm                                                                                                   0.0000 1.6241 
        mult_acc:core/MAC:acc#3                      mgc_add_32_0_32_0_32_2                                                         0.5094 2.1336 
        mult_acc:core/acc.sva#1                                                                                                     0.0000 2.1336 
        mult_acc:core/mux#2                          mgc_mux_32_1_2_3                                                               0.0812 2.2148 
        mult_acc:core/mux#2.itm                                                                                                     0.0000 2.2148 
        mult_acc:core/reg(dout:rsc:mgc_out_stdreg.d) mgc_reg_pos_32_0_0_1_1_0_0_2                                                   0.0000 2.2148 
                                                                                                                                                  
      3                                              mult_acc:core/reg(MAC:i#1.sva#2)  mult_acc:core/reg(acc.sva)                   2.1635 0.8395 
                                                                                                                                                  
        Instance                                     Component                                                                      Delta  Delay  
        --------                                     ---------                                                                      -----  -----  
        mult_acc:core/reg(MAC:i#1.sva#2)             mgc_reg_pos_2_0_0_1_1_0_0_2                                                    0.1207 0.1207 
        mult_acc:core/MAC:i#1.sva#2                                                                                                 0.0000 0.1207 
        mult_acc:core/MAC:mux                        mgc_mux_32_2_4_1                                                               0.0843 0.2051 
        mult_acc:core/MAC:mux.itm                                                                                                   0.0000 0.2051 
        mult_acc:core/MAC:mul                        mgc_mul_32_0_32_0_32_3                                                         1.4191 1.6241 
        mult_acc:core/MAC:mul.itm                                                                                                   0.0000 1.6241 
        mult_acc:core/MAC:acc#3                      mgc_add_32_0_32_0_32_2                                                         0.5094 2.1336 
        mult_acc:core/acc.sva#1                                                                                                     0.0000 2.1336 
        mult_acc:core/and#1                          mgc_and_32_2_4                                                                 0.0299 2.1635 
        mult_acc:core/and#1.itm                                                                                                     0.0000 2.1635 
        mult_acc:core/reg(acc.sva)                   mgc_reg_pos_32_0_0_1_1_0_0_2                                                   0.0000 2.1635 
                                                                                                                                                  
      4                                              mult_acc:core/reg(MAC:i#1.sva#2)  mult_acc:core/reg(acc.sva)                   2.1635 0.8395 
                                                                                                                                                  
        Instance                                     Component                                                                      Delta  Delay  
        --------                                     ---------                                                                      -----  -----  
        mult_acc:core/reg(MAC:i#1.sva#2)             mgc_reg_pos_2_0_0_1_1_0_0_2                                                    0.1207 0.1207 
        mult_acc:core/MAC:i#1.sva#2                                                                                                 0.0000 0.1207 
        mult_acc:core/MAC:mux#1                      mgc_mux_32_2_4_1                                                               0.0843 0.2051 
        mult_acc:core/MAC:mux#1.itm                                                                                                 0.0000 0.2051 
        mult_acc:core/MAC:mul                        mgc_mul_32_0_32_0_32_3                                                         1.4191 1.6241 
        mult_acc:core/MAC:mul.itm                                                                                                   0.0000 1.6241 
        mult_acc:core/MAC:acc#3                      mgc_add_32_0_32_0_32_2                                                         0.5094 2.1336 
        mult_acc:core/acc.sva#1                                                                                                     0.0000 2.1336 
        mult_acc:core/and#1                          mgc_and_32_2_4                                                                 0.0299 2.1635 
        mult_acc:core/and#1.itm                                                                                                     0.0000 2.1635 
        mult_acc:core/reg(acc.sva)                   mgc_reg_pos_32_0_0_1_1_0_0_2                                                   0.0000 2.1635 
                                                                                                                                                  
      5                                              mult_acc:core/a:rsc:mgc_in_wire.d mult_acc:core/reg(acc.sva)                   2.0427 0.9603 
                                                                                                                                                  
        Instance                                     Component                                                                      Delta  Delay  
        --------                                     ---------                                                                      -----  -----  
        mult_acc:core/a:rsc:mgc_in_wire.d                                                                                           0.0000 0.0000 
        mult_acc:core/slc(a:rsc:mgc_in_wire.d)#1                                                                                    0.0000 0.0000 
        mult_acc:core/slc(a:rsc:mgc_in_wire.d)#1.itm                                                                                0.0000 0.0000 
        mult_acc:core/MAC:mux                        mgc_mux_32_2_4_1                                                               0.0843 0.0843 
        mult_acc:core/MAC:mux.itm                                                                                                   0.0000 0.0843 
        mult_acc:core/MAC:mul                        mgc_mul_32_0_32_0_32_3                                                         1.4191 1.5034 
        mult_acc:core/MAC:mul.itm                                                                                                   0.0000 1.5034 
        mult_acc:core/MAC:acc#3                      mgc_add_32_0_32_0_32_2                                                         0.5094 2.0128 
        mult_acc:core/acc.sva#1                                                                                                     0.0000 2.0128 
        mult_acc:core/and#1                          mgc_and_32_2_4                                                                 0.0299 2.0427 
        mult_acc:core/and#1.itm                                                                                                     0.0000 2.0427 
        mult_acc:core/reg(acc.sva)                   mgc_reg_pos_32_0_0_1_1_0_0_2                                                   0.0000 2.0427 
                                                                                                                                                  
      6                                              mult_acc:core/b:rsc:mgc_in_wire.d mult_acc:core/reg(acc.sva)                   2.0427 0.9603 
                                                                                                                                                  
        Instance                                     Component                                                                      Delta  Delay  
        --------                                     ---------                                                                      -----  -----  
        mult_acc:core/b:rsc:mgc_in_wire.d                                                                                           0.0000 0.0000 
        mult_acc:core/slc(b:rsc:mgc_in_wire.d)#2                                                                                    0.0000 0.0000 
        mult_acc:core/slc(b:rsc:mgc_in_wire.d)#2.itm                                                                                0.0000 0.0000 
        mult_acc:core/MAC:mux#1                      mgc_mux_32_2_4_1                                                               0.0843 0.0843 
        mult_acc:core/MAC:mux#1.itm                                                                                                 0.0000 0.0843 
        mult_acc:core/MAC:mul                        mgc_mul_32_0_32_0_32_3                                                         1.4191 1.5034 
        mult_acc:core/MAC:mul.itm                                                                                                   0.0000 1.5034 
        mult_acc:core/MAC:acc#3                      mgc_add_32_0_32_0_32_2                                                         0.5094 2.0128 
        mult_acc:core/acc.sva#1                                                                                                     0.0000 2.0128 
        mult_acc:core/and#1                          mgc_and_32_2_4                                                                 0.0299 2.0427 
        mult_acc:core/and#1.itm                                                                                                     0.0000 2.0427 
        mult_acc:core/reg(acc.sva)                   mgc_reg_pos_32_0_0_1_1_0_0_2                                                   0.0000 2.0427 
                                                                                                                                                  
      7                                              mult_acc:core/a:rsc:mgc_in_wire.d mult_acc:core/reg(acc.sva)                   2.0427 0.9603 
                                                                                                                                                  
        Instance                                     Component                                                                      Delta  Delay  
        --------                                     ---------                                                                      -----  -----  
        mult_acc:core/a:rsc:mgc_in_wire.d                                                                                           0.0000 0.0000 
        mult_acc:core/slc(a:rsc:mgc_in_wire.d)#3                                                                                    0.0000 0.0000 
        mult_acc:core/slc(a:rsc:mgc_in_wire.d)#3.itm                                                                                0.0000 0.0000 
        mult_acc:core/MAC:mux                        mgc_mux_32_2_4_1                                                               0.0843 0.0843 
        mult_acc:core/MAC:mux.itm                                                                                                   0.0000 0.0843 
        mult_acc:core/MAC:mul                        mgc_mul_32_0_32_0_32_3                                                         1.4191 1.5034 
        mult_acc:core/MAC:mul.itm                                                                                                   0.0000 1.5034 
        mult_acc:core/MAC:acc#3                      mgc_add_32_0_32_0_32_2                                                         0.5094 2.0128 
        mult_acc:core/acc.sva#1                                                                                                     0.0000 2.0128 
        mult_acc:core/and#1                          mgc_and_32_2_4                                                                 0.0299 2.0427 
        mult_acc:core/and#1.itm                                                                                                     0.0000 2.0427 
        mult_acc:core/reg(acc.sva)                   mgc_reg_pos_32_0_0_1_1_0_0_2                                                   0.0000 2.0427 
                                                                                                                                                  
      8                                              mult_acc:core/b:rsc:mgc_in_wire.d mult_acc:core/reg(acc.sva)                   2.0427 0.9603 
                                                                                                                                                  
        Instance                                     Component                                                                      Delta  Delay  
        --------                                     ---------                                                                      -----  -----  
        mult_acc:core/b:rsc:mgc_in_wire.d                                                                                           0.0000 0.0000 
        mult_acc:core/slc(b:rsc:mgc_in_wire.d)#1                                                                                    0.0000 0.0000 
        mult_acc:core/slc(b:rsc:mgc_in_wire.d)#1.itm                                                                                0.0000 0.0000 
        mult_acc:core/MAC:mux#1                      mgc_mux_32_2_4_1                                                               0.0843 0.0843 
        mult_acc:core/MAC:mux#1.itm                                                                                                 0.0000 0.0843 
        mult_acc:core/MAC:mul                        mgc_mul_32_0_32_0_32_3                                                         1.4191 1.5034 
        mult_acc:core/MAC:mul.itm                                                                                                   0.0000 1.5034 
        mult_acc:core/MAC:acc#3                      mgc_add_32_0_32_0_32_2                                                         0.5094 2.0128 
        mult_acc:core/acc.sva#1                                                                                                     0.0000 2.0128 
        mult_acc:core/and#1                          mgc_and_32_2_4                                                                 0.0299 2.0427 
        mult_acc:core/and#1.itm                                                                                                     0.0000 2.0427 
        mult_acc:core/reg(acc.sva)                   mgc_reg_pos_32_0_0_1_1_0_0_2                                                   0.0000 2.0427 
                                                                                                                                                  
      9                                              mult_acc:core/a:rsc:mgc_in_wire.d mult_acc:core/reg(acc.sva)                   2.0427 0.9603 
                                                                                                                                                  
        Instance                                     Component                                                                      Delta  Delay  
        --------                                     ---------                                                                      -----  -----  
        mult_acc:core/a:rsc:mgc_in_wire.d                                                                                           0.0000 0.0000 
        mult_acc:core/slc(a:rsc:mgc_in_wire.d)                                                                                      0.0000 0.0000 
        mult_acc:core/slc(a:rsc:mgc_in_wire.d).itm                                                                                  0.0000 0.0000 
        mult_acc:core/MAC:mux                        mgc_mux_32_2_4_1                                                               0.0843 0.0843 
        mult_acc:core/MAC:mux.itm                                                                                                   0.0000 0.0843 
        mult_acc:core/MAC:mul                        mgc_mul_32_0_32_0_32_3                                                         1.4191 1.5034 
        mult_acc:core/MAC:mul.itm                                                                                                   0.0000 1.5034 
        mult_acc:core/MAC:acc#3                      mgc_add_32_0_32_0_32_2                                                         0.5094 2.0128 
        mult_acc:core/acc.sva#1                                                                                                     0.0000 2.0128 
        mult_acc:core/and#1                          mgc_and_32_2_4                                                                 0.0299 2.0427 
        mult_acc:core/and#1.itm                                                                                                     0.0000 2.0427 
        mult_acc:core/reg(acc.sva)                   mgc_reg_pos_32_0_0_1_1_0_0_2                                                   0.0000 2.0427 
                                                                                                                                                  
      10                                             mult_acc:core/b:rsc:mgc_in_wire.d mult_acc:core/reg(acc.sva)                   2.0427 0.9603 
                                                                                                                                                  
        Instance                                     Component                                                                      Delta  Delay  
        --------                                     ---------                                                                      -----  -----  
        mult_acc:core/b:rsc:mgc_in_wire.d                                                                                           0.0000 0.0000 
        mult_acc:core/slc(b:rsc:mgc_in_wire.d)                                                                                      0.0000 0.0000 
        mult_acc:core/slc(b:rsc:mgc_in_wire.d).itm                                                                                  0.0000 0.0000 
        mult_acc:core/MAC:mux#1                      mgc_mux_32_2_4_1                                                               0.0843 0.0843 
        mult_acc:core/MAC:mux#1.itm                                                                                                 0.0000 0.0843 
        mult_acc:core/MAC:mul                        mgc_mul_32_0_32_0_32_3                                                         1.4191 1.5034 
        mult_acc:core/MAC:mul.itm                                                                                                   0.0000 1.5034 
        mult_acc:core/MAC:acc#3                      mgc_add_32_0_32_0_32_2                                                         0.5094 2.0128 
        mult_acc:core/acc.sva#1                                                                                                     0.0000 2.0128 
        mult_acc:core/and#1                          mgc_and_32_2_4                                                                 0.0299 2.0427 
        mult_acc:core/and#1.itm                                                                                                     0.0000 2.0427 
        mult_acc:core/reg(acc.sva)                   mgc_reg_pos_32_0_0_1_1_0_0_2                                                   0.0000 2.0427 
                                                                                                                                                  
      
    Register Input and Register-to-Output Slack
      Clock period or pin-to-reg delay constraint: 3.003003003
      
      Instance                                     Port        Slack (Delay) Messages 
      -------------------------------------------- ---------- ------ ------- --------
      mult_acc:core/reg(MAC:i#1.sva#2)             and.itm    2.6535  0.3495          
      mult_acc:core/reg(acc.sva)                   and#1.itm  0.8395  2.1635          
      mult_acc:core/reg(dout:rsc:mgc_out_stdreg.d) mux#2.itm  0.7882  2.2148          
      mult_acc                                     dout:rsc.z 2.8823  0.1207          
      
  End of Report
