Classic Timing Analyzer report for pwm
Mon Jan 10 09:32:33 2011
Quartus II Version 10.0 Build 218 06/27/2010 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Classic Timing Analyzer Deprecation
  3. Timing Analyzer Summary
  4. Timing Analyzer Settings
  5. Clock Settings Summary
  6. Parallel Compilation
  7. Clock Setup: 'clock'
  8. tco
  9. tpd
 10. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2010 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



---------------------------------------
; Classic Timing Analyzer Deprecation ;
---------------------------------------
Classic Timing Analyzer will not be available in a future release of the Quartus II software. Use the TimeQuest Timing Analyzer to run timing analysis on your design. Convert all the project settings and the timing constraints to TimeQuest Timing Analyzer equivalents.


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                            ;
+------------------------------+-------+---------------+------------------------------------------------+------------------------------------------+------------------------------------------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time                                    ; From                                     ; To                                       ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+------------------------------------------+------------------------------------------+------------+----------+--------------+
; Worst-case tco               ; N/A   ; None          ; 6.983 ns                                       ; sourceSY_count:count|\delay:delay_out[0] ; out                                      ; clock      ; --       ; 0            ;
; Worst-case tpd               ; N/A   ; None          ; 9.356 ns                                       ; samples[0]                               ; out                                      ; --         ; --       ; 0            ;
; Clock Setup: 'clock'         ; N/A   ; None          ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sourceSY_count:count|\delay:delay_out[0] ; sourceSY_count:count|\delay:delay_out[7] ; clock      ; clock    ; 0            ;
; Total number of failed paths ;       ;               ;                                                ;                                          ;                                          ;            ;          ; 0            ;
+------------------------------+-------+---------------+------------------------------------------------+------------------------------------------+------------------------------------------+------------+----------+--------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                                                            ;
+------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                                                               ; Setting            ; From ; To ; Entity Name ;
+------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                                                          ; EP2S15F484C3       ;      ;    ;             ;
; Timing Models                                                                                        ; Final              ;      ;    ;             ;
; Default hold multicycle                                                                              ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                                                            ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                                                               ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                                                       ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                                                                     ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                                                                ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                                                              ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                                                                     ; Off                ;      ;    ;             ;
; Enable Clock Latency                                                                                 ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                                                        ; Off                ;      ;    ;             ;
; Minimum Core Junction Temperature                                                                    ; 0                  ;      ;    ;             ;
; Maximum Core Junction Temperature                                                                    ; 85                 ;      ;    ;             ;
; Number of source nodes to report per destination node                                                ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                                                                ; 10                 ;      ;    ;             ;
; Number of paths to report                                                                            ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                                                         ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                                                               ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                                                           ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                                                         ; On                 ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis                                       ; Off                ;      ;    ;             ;
; Reports worst-case timing paths for each clock domain and analysis                                   ; Off                ;      ;    ;             ;
; Specifies the maximum number of worst-case timing paths to report for each clock domain and analysis ; 100                ;      ;    ;             ;
; Removes common clock path pessimism (CCPP) during slack computation                                  ; Off                ;      ;    ;             ;
+------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clock           ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 4           ;
; Maximum allowed            ; 4           ;
;                            ;             ;
; Average used               ; 1.00        ;
; Maximum used               ; 1           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     1 processor            ; 100.0%      ;
;     2-4 processors         ;   0.0%      ;
+----------------------------+-------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clock'                                                                                                                                                                                                                                     ;
+-------+------------------------------------------------+------------------------------------------+------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From                                     ; To                                       ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+------------------------------------------+------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sourceSY_count:count|\delay:delay_out[0] ; sourceSY_count:count|\delay:delay_out[7] ; clock      ; clock    ; None                        ; None                      ; 1.415 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sourceSY_count:count|\delay:delay_out[1] ; sourceSY_count:count|\delay:delay_out[7] ; clock      ; clock    ; None                        ; None                      ; 1.349 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sourceSY_count:count|\delay:delay_out[2] ; sourceSY_count:count|\delay:delay_out[7] ; clock      ; clock    ; None                        ; None                      ; 1.314 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sourceSY_count:count|\delay:delay_out[3] ; sourceSY_count:count|\delay:delay_out[7] ; clock      ; clock    ; None                        ; None                      ; 1.279 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sourceSY_count:count|\delay:delay_out[4] ; sourceSY_count:count|\delay:delay_out[7] ; clock      ; clock    ; None                        ; None                      ; 1.244 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sourceSY_count:count|\delay:delay_out[5] ; sourceSY_count:count|\delay:delay_out[7] ; clock      ; clock    ; None                        ; None                      ; 1.209 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sourceSY_count:count|\delay:delay_out[7] ; sourceSY_count:count|\delay:delay_out[7] ; clock      ; clock    ; None                        ; None                      ; 1.188 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sourceSY_count:count|\delay:delay_out[6] ; sourceSY_count:count|\delay:delay_out[7] ; clock      ; clock    ; None                        ; None                      ; 1.174 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sourceSY_count:count|\delay:delay_out[0] ; sourceSY_count:count|\delay:delay_out[6] ; clock      ; clock    ; None                        ; None                      ; 0.886 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sourceSY_count:count|\delay:delay_out[0] ; sourceSY_count:count|\delay:delay_out[5] ; clock      ; clock    ; None                        ; None                      ; 0.851 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sourceSY_count:count|\delay:delay_out[1] ; sourceSY_count:count|\delay:delay_out[6] ; clock      ; clock    ; None                        ; None                      ; 0.820 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sourceSY_count:count|\delay:delay_out[0] ; sourceSY_count:count|\delay:delay_out[4] ; clock      ; clock    ; None                        ; None                      ; 0.816 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sourceSY_count:count|\delay:delay_out[1] ; sourceSY_count:count|\delay:delay_out[5] ; clock      ; clock    ; None                        ; None                      ; 0.785 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sourceSY_count:count|\delay:delay_out[2] ; sourceSY_count:count|\delay:delay_out[6] ; clock      ; clock    ; None                        ; None                      ; 0.785 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sourceSY_count:count|\delay:delay_out[0] ; sourceSY_count:count|\delay:delay_out[3] ; clock      ; clock    ; None                        ; None                      ; 0.781 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sourceSY_count:count|\delay:delay_out[1] ; sourceSY_count:count|\delay:delay_out[4] ; clock      ; clock    ; None                        ; None                      ; 0.750 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sourceSY_count:count|\delay:delay_out[2] ; sourceSY_count:count|\delay:delay_out[5] ; clock      ; clock    ; None                        ; None                      ; 0.750 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sourceSY_count:count|\delay:delay_out[3] ; sourceSY_count:count|\delay:delay_out[6] ; clock      ; clock    ; None                        ; None                      ; 0.750 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sourceSY_count:count|\delay:delay_out[0] ; sourceSY_count:count|\delay:delay_out[2] ; clock      ; clock    ; None                        ; None                      ; 0.746 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sourceSY_count:count|\delay:delay_out[1] ; sourceSY_count:count|\delay:delay_out[3] ; clock      ; clock    ; None                        ; None                      ; 0.715 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sourceSY_count:count|\delay:delay_out[2] ; sourceSY_count:count|\delay:delay_out[4] ; clock      ; clock    ; None                        ; None                      ; 0.715 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sourceSY_count:count|\delay:delay_out[3] ; sourceSY_count:count|\delay:delay_out[5] ; clock      ; clock    ; None                        ; None                      ; 0.715 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sourceSY_count:count|\delay:delay_out[4] ; sourceSY_count:count|\delay:delay_out[6] ; clock      ; clock    ; None                        ; None                      ; 0.715 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sourceSY_count:count|\delay:delay_out[0] ; sourceSY_count:count|\delay:delay_out[1] ; clock      ; clock    ; None                        ; None                      ; 0.683 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sourceSY_count:count|\delay:delay_out[1] ; sourceSY_count:count|\delay:delay_out[2] ; clock      ; clock    ; None                        ; None                      ; 0.680 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sourceSY_count:count|\delay:delay_out[2] ; sourceSY_count:count|\delay:delay_out[3] ; clock      ; clock    ; None                        ; None                      ; 0.680 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sourceSY_count:count|\delay:delay_out[3] ; sourceSY_count:count|\delay:delay_out[4] ; clock      ; clock    ; None                        ; None                      ; 0.680 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sourceSY_count:count|\delay:delay_out[4] ; sourceSY_count:count|\delay:delay_out[5] ; clock      ; clock    ; None                        ; None                      ; 0.680 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sourceSY_count:count|\delay:delay_out[5] ; sourceSY_count:count|\delay:delay_out[6] ; clock      ; clock    ; None                        ; None                      ; 0.680 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sourceSY_count:count|\delay:delay_out[1] ; sourceSY_count:count|\delay:delay_out[1] ; clock      ; clock    ; None                        ; None                      ; 0.609 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sourceSY_count:count|\delay:delay_out[2] ; sourceSY_count:count|\delay:delay_out[2] ; clock      ; clock    ; None                        ; None                      ; 0.609 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sourceSY_count:count|\delay:delay_out[3] ; sourceSY_count:count|\delay:delay_out[3] ; clock      ; clock    ; None                        ; None                      ; 0.609 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sourceSY_count:count|\delay:delay_out[4] ; sourceSY_count:count|\delay:delay_out[4] ; clock      ; clock    ; None                        ; None                      ; 0.609 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sourceSY_count:count|\delay:delay_out[5] ; sourceSY_count:count|\delay:delay_out[5] ; clock      ; clock    ; None                        ; None                      ; 0.609 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sourceSY_count:count|\delay:delay_out[6] ; sourceSY_count:count|\delay:delay_out[6] ; clock      ; clock    ; None                        ; None                      ; 0.609 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; sourceSY_count:count|\delay:delay_out[0] ; sourceSY_count:count|\delay:delay_out[0] ; clock      ; clock    ; None                        ; None                      ; 0.488 ns                ;
+-------+------------------------------------------------+------------------------------------------+------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-------------------------------------------------------------------------------------------------+
; tco                                                                                             ;
+-------+--------------+------------+------------------------------------------+-----+------------+
; Slack ; Required tco ; Actual tco ; From                                     ; To  ; From Clock ;
+-------+--------------+------------+------------------------------------------+-----+------------+
; N/A   ; None         ; 6.983 ns   ; sourceSY_count:count|\delay:delay_out[0] ; out ; clock      ;
; N/A   ; None         ; 6.727 ns   ; sourceSY_count:count|\delay:delay_out[1] ; out ; clock      ;
; N/A   ; None         ; 6.693 ns   ; sourceSY_count:count|\delay:delay_out[5] ; out ; clock      ;
; N/A   ; None         ; 6.615 ns   ; sourceSY_count:count|\delay:delay_out[6] ; out ; clock      ;
; N/A   ; None         ; 6.360 ns   ; sourceSY_count:count|\delay:delay_out[7] ; out ; clock      ;
; N/A   ; None         ; 6.057 ns   ; sourceSY_count:count|\delay:delay_out[2] ; out ; clock      ;
; N/A   ; None         ; 5.971 ns   ; sourceSY_count:count|\delay:delay_out[3] ; out ; clock      ;
; N/A   ; None         ; 5.949 ns   ; sourceSY_count:count|\delay:delay_out[4] ; out ; clock      ;
+-------+--------------+------------+------------------------------------------+-----+------------+


+----------------------------------------------------------------+
; tpd                                                            ;
+-------+-------------------+-----------------+------------+-----+
; Slack ; Required P2P Time ; Actual P2P Time ; From       ; To  ;
+-------+-------------------+-----------------+------------+-----+
; N/A   ; None              ; 9.356 ns        ; samples[0] ; out ;
; N/A   ; None              ; 9.191 ns        ; samples[1] ; out ;
; N/A   ; None              ; 8.715 ns        ; samples[7] ; out ;
; N/A   ; None              ; 8.587 ns        ; samples[5] ; out ;
; N/A   ; None              ; 8.459 ns        ; samples[2] ; out ;
; N/A   ; None              ; 8.416 ns        ; samples[6] ; out ;
; N/A   ; None              ; 8.398 ns        ; samples[3] ; out ;
; N/A   ; None              ; 7.461 ns        ; samples[4] ; out ;
+-------+-------------------+-----------------+------------+-----+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 10.0 Build 218 06/27/2010 SJ Web Edition
    Info: Processing started: Mon Jan 10 09:32:32 2011
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off pwm -c pwm --timing_analysis_only
Warning: Classic Timing Analyzer will not be available in a future release of the Quartus II software. Use the TimeQuest Timing Analyzer to run timing analysis on your design. Convert all the project settings and the timing constraints to TimeQuest Timing Analyzer equivalents.
Info: Parallel compilation is enabled and will use 4 of the 4 processors detected
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clock" is an undefined clock
Info: Clock "clock" Internal fmax is restricted to 500.0 MHz between source register "sourceSY_count:count|\delay:delay_out[0]" and destination register "sourceSY_count:count|\delay:delay_out[7]"
    Info: fmax restricted to clock pin edge rate 2.0 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.415 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X13_Y1_N1; Fanout = 4; REG Node = 'sourceSY_count:count|\delay:delay_out[0]'
            Info: 2: + IC(0.215 ns) + CELL(0.309 ns) = 0.524 ns; Loc. = LCCOMB_X13_Y1_N16; Fanout = 2; COMB Node = 'sourceSY_count:count|Add0~2'
            Info: 3: + IC(0.000 ns) + CELL(0.035 ns) = 0.559 ns; Loc. = LCCOMB_X13_Y1_N18; Fanout = 2; COMB Node = 'sourceSY_count:count|Add0~6'
            Info: 4: + IC(0.000 ns) + CELL(0.035 ns) = 0.594 ns; Loc. = LCCOMB_X13_Y1_N20; Fanout = 2; COMB Node = 'sourceSY_count:count|Add0~10'
            Info: 5: + IC(0.000 ns) + CELL(0.035 ns) = 0.629 ns; Loc. = LCCOMB_X13_Y1_N22; Fanout = 2; COMB Node = 'sourceSY_count:count|Add0~14'
            Info: 6: + IC(0.000 ns) + CELL(0.035 ns) = 0.664 ns; Loc. = LCCOMB_X13_Y1_N24; Fanout = 2; COMB Node = 'sourceSY_count:count|Add0~18'
            Info: 7: + IC(0.000 ns) + CELL(0.035 ns) = 0.699 ns; Loc. = LCCOMB_X13_Y1_N26; Fanout = 1; COMB Node = 'sourceSY_count:count|Add0~22'
            Info: 8: + IC(0.000 ns) + CELL(0.125 ns) = 0.824 ns; Loc. = LCCOMB_X13_Y1_N28; Fanout = 1; COMB Node = 'sourceSY_count:count|Add0~25'
            Info: 9: + IC(0.383 ns) + CELL(0.053 ns) = 1.260 ns; Loc. = LCCOMB_X13_Y1_N30; Fanout = 1; COMB Node = 'sourceSY_count:count|\delay:delay_out[7]~0'
            Info: 10: + IC(0.000 ns) + CELL(0.155 ns) = 1.415 ns; Loc. = LCFF_X13_Y1_N31; Fanout = 3; REG Node = 'sourceSY_count:count|\delay:delay_out[7]'
            Info: Total cell delay = 0.817 ns ( 57.74 % )
            Info: Total interconnect delay = 0.598 ns ( 42.26 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clock" to destination register is 2.421 ns
                Info: 1: + IC(0.000 ns) + CELL(0.809 ns) = 0.809 ns; Loc. = PIN_AB13; Fanout = 1; CLK Node = 'clock'
                Info: 2: + IC(0.354 ns) + CELL(0.000 ns) = 1.163 ns; Loc. = CLKCTRL_G5; Fanout = 8; COMB Node = 'clock~clkctrl'
                Info: 3: + IC(0.640 ns) + CELL(0.618 ns) = 2.421 ns; Loc. = LCFF_X13_Y1_N31; Fanout = 3; REG Node = 'sourceSY_count:count|\delay:delay_out[7]'
                Info: Total cell delay = 1.427 ns ( 58.94 % )
                Info: Total interconnect delay = 0.994 ns ( 41.06 % )
            Info: - Longest clock path from clock "clock" to source register is 2.421 ns
                Info: 1: + IC(0.000 ns) + CELL(0.809 ns) = 0.809 ns; Loc. = PIN_AB13; Fanout = 1; CLK Node = 'clock'
                Info: 2: + IC(0.354 ns) + CELL(0.000 ns) = 1.163 ns; Loc. = CLKCTRL_G5; Fanout = 8; COMB Node = 'clock~clkctrl'
                Info: 3: + IC(0.640 ns) + CELL(0.618 ns) = 2.421 ns; Loc. = LCFF_X13_Y1_N1; Fanout = 4; REG Node = 'sourceSY_count:count|\delay:delay_out[0]'
                Info: Total cell delay = 1.427 ns ( 58.94 % )
                Info: Total interconnect delay = 0.994 ns ( 41.06 % )
        Info: + Micro clock to output delay of source is 0.094 ns
        Info: + Micro setup delay of destination is 0.090 ns
Info: tco from clock "clock" to destination pin "out" through register "sourceSY_count:count|\delay:delay_out[0]" is 6.983 ns
    Info: + Longest clock path from clock "clock" to source register is 2.421 ns
        Info: 1: + IC(0.000 ns) + CELL(0.809 ns) = 0.809 ns; Loc. = PIN_AB13; Fanout = 1; CLK Node = 'clock'
        Info: 2: + IC(0.354 ns) + CELL(0.000 ns) = 1.163 ns; Loc. = CLKCTRL_G5; Fanout = 8; COMB Node = 'clock~clkctrl'
        Info: 3: + IC(0.640 ns) + CELL(0.618 ns) = 2.421 ns; Loc. = LCFF_X13_Y1_N1; Fanout = 4; REG Node = 'sourceSY_count:count|\delay:delay_out[0]'
        Info: Total cell delay = 1.427 ns ( 58.94 % )
        Info: Total interconnect delay = 0.994 ns ( 41.06 % )
    Info: + Micro clock to output delay of source is 0.094 ns
    Info: + Longest register to pin delay is 4.468 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X13_Y1_N1; Fanout = 4; REG Node = 'sourceSY_count:count|\delay:delay_out[0]'
        Info: 2: + IC(0.304 ns) + CELL(0.225 ns) = 0.529 ns; Loc. = LCCOMB_X13_Y1_N2; Fanout = 1; COMB Node = 'LessThan0~0'
        Info: 3: + IC(0.405 ns) + CELL(0.357 ns) = 1.291 ns; Loc. = LCCOMB_X13_Y1_N6; Fanout = 1; COMB Node = 'LessThan0~1'
        Info: 4: + IC(0.466 ns) + CELL(0.053 ns) = 1.810 ns; Loc. = LCCOMB_X11_Y1_N18; Fanout = 1; COMB Node = 'LessThan0~4'
        Info: 5: + IC(0.666 ns) + CELL(1.992 ns) = 4.468 ns; Loc. = PIN_AB16; Fanout = 0; PIN Node = 'out'
        Info: Total cell delay = 2.627 ns ( 58.80 % )
        Info: Total interconnect delay = 1.841 ns ( 41.20 % )
Info: Longest tpd from source pin "samples[0]" to destination pin "out" is 9.356 ns
    Info: 1: + IC(0.000 ns) + CELL(0.837 ns) = 0.837 ns; Loc. = PIN_W16; Fanout = 1; PIN Node = 'samples[0]'
    Info: 2: + IC(4.214 ns) + CELL(0.366 ns) = 5.417 ns; Loc. = LCCOMB_X13_Y1_N2; Fanout = 1; COMB Node = 'LessThan0~0'
    Info: 3: + IC(0.405 ns) + CELL(0.357 ns) = 6.179 ns; Loc. = LCCOMB_X13_Y1_N6; Fanout = 1; COMB Node = 'LessThan0~1'
    Info: 4: + IC(0.466 ns) + CELL(0.053 ns) = 6.698 ns; Loc. = LCCOMB_X11_Y1_N18; Fanout = 1; COMB Node = 'LessThan0~4'
    Info: 5: + IC(0.666 ns) + CELL(1.992 ns) = 9.356 ns; Loc. = PIN_AB16; Fanout = 0; PIN Node = 'out'
    Info: Total cell delay = 3.605 ns ( 38.53 % )
    Info: Total interconnect delay = 5.751 ns ( 61.47 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Peak virtual memory: 193 megabytes
    Info: Processing ended: Mon Jan 10 09:32:33 2011
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:00


