PriorityScheduler Project Status (06/09/2011 - 17:29:59)
Project File: EPOSScheduler.xise Parser Errors:
Module Name: PriorityScheduler Implementation State: Mapped
Target Device: xc6vlx240t-3ff1156
  • Errors:
No Errors
Product Version:ISE 13.1
  • Warnings:
1 Warning (1 new)
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 832 301,440 1%  
    Number used as Flip Flops 832      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 1,250 150,720 1%  
    Number used as logic 1,236 150,720 1%  
        Number using O6 output only 1,060      
        Number using O5 output only 1      
        Number using O5 and O6 175      
        Number used as ROM 0      
    Number used as Memory 0 58,400 0%  
    Number used exclusively as route-thrus 14      
        Number with same-slice register load 14      
        Number with same-slice carry load 0      
        Number with other load 0      
Number of occupied Slices 564 37,680 1%  
Number of LUT Flip Flop pairs used 1,653      
    Number with an unused Flip Flop 836 1,653 50%  
    Number with an unused LUT 403 1,653 24%  
    Number of fully used LUT-FF pairs 414 1,653 25%  
    Number of unique control sets 58      
    Number of slice register sites lost
        to control set restrictions
120 301,440 1%  
Number of bonded IOBs 93 600 15%  
Number of RAMB36E1/FIFO36E1s 0 416 0%  
Number of RAMB18E1/FIFO18E1s 0 832 0%  
Number of BUFG/BUFGCTRLs 1 32 3%  
    Number used as BUFGs 1      
    Number used as BUFGCTRLs 0      
Number of ILOGICE1/ISERDESE1s 0 720 0%  
Number of OLOGICE1/OSERDESE1s 0 720 0%  
Number of BSCANs 0 4 0%  
Number of BUFHCEs 0 144 0%  
Number of BUFOs 0 36 0%  
Number of BUFIODQSs 0 72 0%  
Number of BUFRs 0 36 0%  
Number of CAPTUREs 0 1 0%  
Number of DSP48E1s 0 768 0%  
Number of EFUSE_USRs 0 1 0%  
Number of FRAME_ECCs 0 1 0%  
Number of GTXE1s 0 20 0%  
Number of IBUFDS_GTXE1s 0 12 0%  
Number of ICAPs 0 2 0%  
Number of IDELAYCTRLs 0 18 0%  
Number of IODELAYE1s 0 720 0%  
Number of MMCM_ADVs 0 12 0%  
Number of PCIE_2_0s 0 2 0%  
Number of STARTUPs 1 1 100%  
Number of SYSMONs 0 1 0%  
Number of TEMAC_SINGLEs 0 4 0%  
Average Fanout of Non-Clock Nets 4.66      
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentThu Jun 9 17:28:08 201101 Warning (1 new)6 Infos (6 new)
Translation ReportCurrentThu Jun 9 17:28:13 2011000
Map ReportCurrentThu Jun 9 17:29:57 2011006 Infos (6 new)
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 06/09/2011 - 17:29:59