Classic Timing Analyzer report for bc
Fri Nov 23 22:04:31 2007
Quartus II Version 7.1 Build 178 06/25/2007 Service Pack 1 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'clk'
  6. tsu
  7. tco
  8. th
  9. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                            ;
+------------------------------+-------+---------------+------------------------------------------------+------------------+------------------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time                                    ; From             ; To               ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+------------------+------------------+------------+----------+--------------+
; Worst-case tsu               ; N/A   ; None          ; 2.998 ns                                       ; inicio           ; estado.primeiro1 ; --         ; clk      ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 6.832 ns                                       ; estado.segundo2  ; n                ; clk        ; --       ; 0            ;
; Worst-case th                ; N/A   ; None          ; -2.626 ns                                      ; inicio           ; estado.espera    ; --         ; clk      ; 0            ;
; Clock Setup: 'clk'           ; N/A   ; None          ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; estado.terceiro1 ; estado.primeiro2 ; clk        ; clk      ; 0            ;
; Total number of failed paths ;       ;               ;                                                ;                  ;                  ;            ;          ; 0            ;
+------------------------------+-------+---------------+------------------------------------------------+------------------+------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP2S15F484C3       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                                                               ;
+-------+------------------------------------------------+------------------------------+------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From                         ; To                           ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+------------------------------+------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; estado.terceiro1             ; estado.primeiro2             ; clk        ; clk      ; None                        ; None                      ; 1.105 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; estado.terceiro1             ; estado.primeiro1             ; clk        ; clk      ; None                        ; None                      ; 1.046 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; estado.primeiro2             ; estado.primeiro2             ; clk        ; clk      ; None                        ; None                      ; 1.017 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; estado.final                 ; estado.primeiro2             ; clk        ; clk      ; None                        ; None                      ; 0.963 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; contadorSeis:contador_6|n[2] ; estado.segundo2              ; clk        ; clk      ; None                        ; None                      ; 0.962 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; estado.final                 ; estado.primeiro1             ; clk        ; clk      ; None                        ; None                      ; 0.904 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; estado.primeiro1             ; estado.primeiro2             ; clk        ; clk      ; None                        ; None                      ; 0.904 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; estado.segundo1              ; estado.primeiro2             ; clk        ; clk      ; None                        ; None                      ; 0.901 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; estado.final                 ; estado.espera                ; clk        ; clk      ; None                        ; None                      ; 0.866 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; contadorSeis:contador_6|n[1] ; estado.terceiro1             ; clk        ; clk      ; None                        ; None                      ; 0.861 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; contadorSeis:contador_6|n[2] ; estado.primeiro2             ; clk        ; clk      ; None                        ; None                      ; 0.860 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; estado.segundo1              ; estado.primeiro1             ; clk        ; clk      ; None                        ; None                      ; 0.842 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; contadorSeis:contador_6|n[0] ; estado.segundo1              ; clk        ; clk      ; None                        ; None                      ; 0.824 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; contadorSeis:contador_6|n[1] ; estado.primeiro2             ; clk        ; clk      ; None                        ; None                      ; 0.813 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; contadorSeis:contador_6|n[2] ; estado.terceiro1             ; clk        ; clk      ; None                        ; None                      ; 0.799 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; estado.espera                ; estado.primeiro1             ; clk        ; clk      ; None                        ; None                      ; 0.799 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; contadorSeis:contador_6|n[0] ; contadorSeis:contador_6|n[2] ; clk        ; clk      ; None                        ; None                      ; 0.795 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; estado.segundo1              ; estado.segundo2              ; clk        ; clk      ; None                        ; None                      ; 0.768 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; contadorDois:contador_2|n[0] ; estado.primeiro2             ; clk        ; clk      ; None                        ; None                      ; 0.754 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; contadorSeis:contador_6|n[1] ; estado.segundo1              ; clk        ; clk      ; None                        ; None                      ; 0.732 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; contadorDois:contador_2|n[0] ; estado.primeiro1             ; clk        ; clk      ; None                        ; None                      ; 0.717 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; contadorSeis:contador_6|n[0] ; estado.segundo2              ; clk        ; clk      ; None                        ; None                      ; 0.656 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; contadorSeis:contador_6|n[0] ; estado.primeiro2             ; clk        ; clk      ; None                        ; None                      ; 0.634 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; contadorSeis:contador_6|n[0] ; estado.terceiro1             ; clk        ; clk      ; None                        ; None                      ; 0.630 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; contadorSeis:contador_6|n[2] ; estado.segundo1              ; clk        ; clk      ; None                        ; None                      ; 0.612 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; contadorSeis:contador_6|n[0] ; contadorSeis:contador_6|n[1] ; clk        ; clk      ; None                        ; None                      ; 0.581 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; estado.primeiro2             ; estado.segundo1              ; clk        ; clk      ; None                        ; None                      ; 0.526 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; estado.terceiro1             ; estado.final                 ; clk        ; clk      ; None                        ; None                      ; 0.521 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; estado.espera                ; estado.espera                ; clk        ; clk      ; None                        ; None                      ; 0.488 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; contadorSeis:contador_6|n[1] ; contadorSeis:contador_6|n[1] ; clk        ; clk      ; None                        ; None                      ; 0.488 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; contadorSeis:contador_6|n[2] ; contadorSeis:contador_6|n[2] ; clk        ; clk      ; None                        ; None                      ; 0.488 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; contadorSeis:contador_6|n[0] ; contadorSeis:contador_6|n[0] ; clk        ; clk      ; None                        ; None                      ; 0.488 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; estado.segundo2              ; estado.segundo2              ; clk        ; clk      ; None                        ; None                      ; 0.488 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; estado.primeiro1             ; estado.primeiro1             ; clk        ; clk      ; None                        ; None                      ; 0.488 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; contadorSeis:contador_6|n[1] ; estado.segundo2              ; clk        ; clk      ; None                        ; None                      ; 0.451 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; contadorSeis:contador_6|n[1] ; contadorSeis:contador_6|n[2] ; clk        ; clk      ; None                        ; None                      ; 0.440 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; estado.segundo2              ; estado.terceiro1             ; clk        ; clk      ; None                        ; None                      ; 0.419 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; contadorDois:contador_2|n[0] ; contadorDois:contador_2|n[0] ; clk        ; clk      ; None                        ; None                      ; 0.396 ns                ;
+-------+------------------------------------------------+------------------------------+------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+--------------------------------------------------------------------------+
; tsu                                                                      ;
+-------+--------------+------------+--------+------------------+----------+
; Slack ; Required tsu ; Actual tsu ; From   ; To               ; To Clock ;
+-------+--------------+------------+--------+------------------+----------+
; N/A   ; None         ; 2.998 ns   ; inicio ; estado.primeiro1 ; clk      ;
; N/A   ; None         ; 2.865 ns   ; inicio ; estado.espera    ; clk      ;
+-------+--------------+------------+--------+------------------+----------+


+-------------------------------------------------------------------------+
; tco                                                                     ;
+-------+--------------+------------+------------------+-----+------------+
; Slack ; Required tco ; Actual tco ; From             ; To  ; From Clock ;
+-------+--------------+------------+------------------+-----+------------+
; N/A   ; None         ; 6.832 ns   ; estado.segundo2  ; n   ; clk        ;
; N/A   ; None         ; 6.630 ns   ; estado.primeiro2 ; n   ; clk        ;
; N/A   ; None         ; 6.277 ns   ; estado.espera    ; sel ; clk        ;
; N/A   ; None         ; 5.918 ns   ; estado.final     ; fim ; clk        ;
+-------+--------------+------------+------------------+-----+------------+


+--------------------------------------------------------------------------------+
; th                                                                             ;
+---------------+-------------+-----------+--------+------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From   ; To               ; To Clock ;
+---------------+-------------+-----------+--------+------------------+----------+
; N/A           ; None        ; -2.626 ns ; inicio ; estado.espera    ; clk      ;
; N/A           ; None        ; -2.759 ns ; inicio ; estado.primeiro1 ; clk      ;
+---------------+-------------+-----------+--------+------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.1 Build 178 06/25/2007 Service Pack 1 SJ Web Edition
    Info: Processing started: Fri Nov 23 22:04:30 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off bc -c bc --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 500.0 MHz between source register "estado.terceiro1" and destination register "estado.primeiro2"
    Info: fmax restricted to clock pin edge rate 2.0 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.105 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X22_Y10_N13; Fanout = 2; REG Node = 'estado.terceiro1'
            Info: 2: + IC(0.247 ns) + CELL(0.228 ns) = 0.475 ns; Loc. = LCCOMB_X22_Y10_N28; Fanout = 2; COMB Node = 'Selector2~159'
            Info: 3: + IC(0.247 ns) + CELL(0.228 ns) = 0.950 ns; Loc. = LCCOMB_X22_Y10_N22; Fanout = 1; COMB Node = 'Selector2~160'
            Info: 4: + IC(0.000 ns) + CELL(0.155 ns) = 1.105 ns; Loc. = LCFF_X22_Y10_N23; Fanout = 4; REG Node = 'estado.primeiro2'
            Info: Total cell delay = 0.611 ns ( 55.29 % )
            Info: Total interconnect delay = 0.494 ns ( 44.71 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.480 ns
                Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 11; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.665 ns) + CELL(0.618 ns) = 2.480 ns; Loc. = LCFF_X22_Y10_N23; Fanout = 4; REG Node = 'estado.primeiro2'
                Info: Total cell delay = 1.472 ns ( 59.35 % )
                Info: Total interconnect delay = 1.008 ns ( 40.65 % )
            Info: - Longest clock path from clock "clk" to source register is 2.480 ns
                Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 11; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.665 ns) + CELL(0.618 ns) = 2.480 ns; Loc. = LCFF_X22_Y10_N13; Fanout = 2; REG Node = 'estado.terceiro1'
                Info: Total cell delay = 1.472 ns ( 59.35 % )
                Info: Total interconnect delay = 1.008 ns ( 40.65 % )
        Info: + Micro clock to output delay of source is 0.094 ns
        Info: + Micro setup delay of destination is 0.090 ns
Info: tsu for register "estado.primeiro1" (data pin = "inicio", clock pin = "clk") is 2.998 ns
    Info: + Longest pin to register delay is 5.388 ns
        Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_N1; Fanout = 2; PIN Node = 'inicio'
        Info: 2: + IC(4.023 ns) + CELL(0.346 ns) = 5.233 ns; Loc. = LCCOMB_X22_Y10_N30; Fanout = 1; COMB Node = 'Selector1~114'
        Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 5.388 ns; Loc. = LCFF_X22_Y10_N31; Fanout = 4; REG Node = 'estado.primeiro1'
        Info: Total cell delay = 1.365 ns ( 25.33 % )
        Info: Total interconnect delay = 4.023 ns ( 74.67 % )
    Info: + Micro setup delay of destination is 0.090 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.480 ns
        Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 11; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.665 ns) + CELL(0.618 ns) = 2.480 ns; Loc. = LCFF_X22_Y10_N31; Fanout = 4; REG Node = 'estado.primeiro1'
        Info: Total cell delay = 1.472 ns ( 59.35 % )
        Info: Total interconnect delay = 1.008 ns ( 40.65 % )
Info: tco from clock "clk" to destination pin "n" through register "estado.segundo2" is 6.832 ns
    Info: + Longest clock path from clock "clk" to source register is 2.480 ns
        Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 11; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.665 ns) + CELL(0.618 ns) = 2.480 ns; Loc. = LCFF_X22_Y10_N1; Fanout = 3; REG Node = 'estado.segundo2'
        Info: Total cell delay = 1.472 ns ( 59.35 % )
        Info: Total interconnect delay = 1.008 ns ( 40.65 % )
    Info: + Micro clock to output delay of source is 0.094 ns
    Info: + Longest register to pin delay is 4.258 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X22_Y10_N1; Fanout = 3; REG Node = 'estado.segundo2'
        Info: 2: + IC(0.342 ns) + CELL(0.228 ns) = 0.570 ns; Loc. = LCCOMB_X22_Y10_N24; Fanout = 1; COMB Node = 'n~0'
        Info: 3: + IC(1.690 ns) + CELL(1.998 ns) = 4.258 ns; Loc. = PIN_C11; Fanout = 0; PIN Node = 'n'
        Info: Total cell delay = 2.226 ns ( 52.28 % )
        Info: Total interconnect delay = 2.032 ns ( 47.72 % )
Info: th for register "estado.espera" (data pin = "inicio", clock pin = "clk") is -2.626 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.480 ns
        Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 11; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.665 ns) + CELL(0.618 ns) = 2.480 ns; Loc. = LCFF_X22_Y10_N27; Fanout = 3; REG Node = 'estado.espera'
        Info: Total cell delay = 1.472 ns ( 59.35 % )
        Info: Total interconnect delay = 1.008 ns ( 40.65 % )
    Info: + Micro hold delay of destination is 0.149 ns
    Info: - Shortest pin to register delay is 5.255 ns
        Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_N1; Fanout = 2; PIN Node = 'inicio'
        Info: 2: + IC(4.008 ns) + CELL(0.228 ns) = 5.100 ns; Loc. = LCCOMB_X22_Y10_N26; Fanout = 1; COMB Node = 'Selector0~26'
        Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 5.255 ns; Loc. = LCFF_X22_Y10_N27; Fanout = 3; REG Node = 'estado.espera'
        Info: Total cell delay = 1.247 ns ( 23.73 % )
        Info: Total interconnect delay = 4.008 ns ( 76.27 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 109 megabytes of memory during processing
    Info: Processing ended: Fri Nov 23 22:04:31 2007
    Info: Elapsed time: 00:00:01


