Analysis & Synthesis report for maquinaMercenaria
Fri Sep 21 18:53:59 2007
Quartus II Version 7.1 Build 178 06/25/2007 Service Pack 1 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. State Machine - |maquinaMercenaria|estado
  8. General Register Statistics
  9. Multiplexer Restructuring Statistics (Restructuring Performed)
 10. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+----------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                               ;
+-----------------------------+----------------------------------------------+
; Analysis & Synthesis Status ; Successful - Fri Sep 21 18:53:59 2007        ;
; Quartus II Version          ; 7.1 Build 178 06/25/2007 SP 1 SJ Web Edition ;
; Revision Name               ; maquinaMercenaria                            ;
; Top-level Entity Name       ; maquinaMercenaria                            ;
; Family                      ; Stratix                                      ;
; Total logic elements        ; 8                                            ;
; Total pins                  ; 5                                            ;
; Total virtual pins          ; 0                                            ;
; Total memory bits           ; 0                                            ;
; DSP block 9-bit elements    ; 0                                            ;
; Total PLLs                  ; 0                                            ;
; Total DLLs                  ; 0                                            ;
+-----------------------------+----------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                            ;
+--------------------------------------------------------------------------------+--------------------+--------------------+
; Option                                                                         ; Setting            ; Default Value      ;
+--------------------------------------------------------------------------------+--------------------+--------------------+
; Top-level entity name                                                          ; maquinaMercenaria  ; maquinaMercenaria  ;
; Family name                                                                    ; Stratix            ; Stratix II         ;
; Restructure Multiplexers                                                       ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                            ; Off                ; Off                ;
; Preserve fewer node names                                                      ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                                      ; Off                ; Off                ;
; Verilog Version                                                                ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                                   ; VHDL93             ; VHDL93             ;
; State Machine Processing                                                       ; Auto               ; Auto               ;
; Safe State Machine                                                             ; Off                ; Off                ;
; Extract Verilog State Machines                                                 ; On                 ; On                 ;
; Extract VHDL State Machines                                                    ; On                 ; On                 ;
; Ignore Verilog initial constructs                                              ; Off                ; Off                ;
; Add Pass-Through Logic to Inferred RAMs                                        ; On                 ; On                 ;
; DSP Block Balancing                                                            ; Auto               ; Auto               ;
; NOT Gate Push-Back                                                             ; On                 ; On                 ;
; Power-Up Don't Care                                                            ; On                 ; On                 ;
; Remove Redundant Logic Cells                                                   ; Off                ; Off                ;
; Remove Duplicate Registers                                                     ; On                 ; On                 ;
; Ignore CARRY Buffers                                                           ; Off                ; Off                ;
; Ignore CASCADE Buffers                                                         ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                                          ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                                      ; Off                ; Off                ;
; Ignore LCELL Buffers                                                           ; Off                ; Off                ;
; Ignore SOFT Buffers                                                            ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                                 ; Off                ; Off                ;
; Optimization Technique -- Stratix/Stratix GX                                   ; Balanced           ; Balanced           ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II/Cyclone III ; 70                 ; 70                 ;
; Auto Carry Chains                                                              ; On                 ; On                 ;
; Auto Open-Drain Pins                                                           ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                                          ; Off                ; Off                ;
; Perform gate-level register retiming                                           ; Off                ; Off                ;
; Allow register retiming to trade off Tsu/Tco with Fmax                         ; On                 ; On                 ;
; Auto ROM Replacement                                                           ; On                 ; On                 ;
; Auto RAM Replacement                                                           ; On                 ; On                 ;
; Auto DSP Block Replacement                                                     ; On                 ; On                 ;
; Auto Shift Register Replacement                                                ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                                  ; On                 ; On                 ;
; Allow Synchronous Control Signals                                              ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                                         ; Off                ; Off                ;
; Auto RAM Block Balancing                                                       ; On                 ; On                 ;
; Auto RAM to Logic Cell Conversion                                              ; Off                ; Off                ;
; Auto Resource Sharing                                                          ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                             ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                             ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                                  ; Off                ; Off                ;
; Ignore translate_off and synthesis_off directives                              ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report                             ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                             ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                               ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                                   ; Normal compilation ; Normal compilation ;
; HDL message level                                                              ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                                ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                       ; 100                ; 100                ;
; Clock MUX Protection                                                           ; On                 ; On                 ;
; Use smart compilation                                                          ; Off                ; Off                ;
+--------------------------------------------------------------------------------+--------------------+--------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                        ;
+----------------------------------+-----------------+-----------+----------------------------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path                                                                 ;
+----------------------------------+-----------------+-----------+----------------------------------------------------------------------------------------------+
; maquinaMercenaria.vhd            ; yes             ; Other     ; E:/UFSC/Semestres/2o. semestre/INE5406/projetos_vhdl/maquinaMercenaria/maquinaMercenaria.vhd ;
+----------------------------------+-----------------+-----------+----------------------------------------------------------------------------------------------+


+-----------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary               ;
+---------------------------------------------+-------------+
; Resource                                    ; Usage       ;
+---------------------------------------------+-------------+
; Total logic elements                        ; 8           ;
;     -- Combinational with no register       ; 4           ;
;     -- Register only                        ; 0           ;
;     -- Combinational with a register        ; 4           ;
;                                             ;             ;
; Logic element usage by number of LUT inputs ;             ;
;     -- 4 input functions                    ; 6           ;
;     -- 3 input functions                    ; 1           ;
;     -- 2 input functions                    ; 1           ;
;     -- 1 input functions                    ; 0           ;
;     -- 0 input functions                    ; 0           ;
;                                             ;             ;
; Logic elements by mode                      ;             ;
;     -- normal mode                          ; 8           ;
;     -- arithmetic mode                      ; 0           ;
;     -- qfbk mode                            ; 0           ;
;     -- register cascade mode                ; 0           ;
;     -- synchronous clear/load mode          ; 0           ;
;     -- asynchronous clear/load mode         ; 4           ;
;                                             ;             ;
; Total registers                             ; 4           ;
; I/O pins                                    ; 5           ;
; Maximum fan-out node                        ; estado.zero ;
; Maximum fan-out                             ; 5           ;
; Total fan-out                               ; 38          ;
; Average fan-out                             ; 2.92        ;
+---------------------------------------------+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                    ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; |maquinaMercenaria         ; 8 (8)       ; 4            ; 0           ; 0            ; 0       ; 0         ; 0         ; 5    ; 0            ; 4 (4)        ; 0 (0)             ; 4 (4)            ; 0 (0)           ; 0 (0)      ; |maquinaMercenaria  ; work         ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


Encoding Type:  One-Hot
+--------------------------------------------------------------------------------------+
; State Machine - |maquinaMercenaria|estado                                            ;
+--------------------+--------------------+-----------+------------------+-------------+
; Name               ; estado.umcinquenta ; estado.um ; estado.cinquenta ; estado.zero ;
+--------------------+--------------------+-----------+------------------+-------------+
; estado.zero        ; 0                  ; 0         ; 0                ; 0           ;
; estado.cinquenta   ; 0                  ; 0         ; 1                ; 1           ;
; estado.um          ; 0                  ; 1         ; 0                ; 1           ;
; estado.umcinquenta ; 1                  ; 0         ; 0                ; 1           ;
+--------------------+--------------------+-----------+------------------+-------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 4     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 4     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                             ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output   ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------+
; 9:1                ; 2 bits    ; 12 LEs        ; 8 LEs                ; 4 LEs                  ; No         ; |maquinaMercenaria|Selector2 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.1 Build 178 06/25/2007 Service Pack 1 SJ Web Edition
    Info: Processing started: Fri Sep 21 18:53:55 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off maquinaMercenaria -c maquinaMercenaria
Warning: Can't analyze file -- file C:/Documents and Settings/Jdas/Desktop/maquinaMercenaria/maquinaMercenaria.vhd is missing
Warning: Using design file maquinaMercenaria.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: maquinaMercenaria-comportamento
    Info: Found entity 1: maquinaMercenaria
Info: Elaborating entity "maquinaMercenaria" for the top level hierarchy
Info: State machine "|maquinaMercenaria|estado" contains 4 states
Info: Selected Auto state machine encoding method for state machine "|maquinaMercenaria|estado"
Info: Encoding result for state machine "|maquinaMercenaria|estado"
    Info: Completed encoding using 4 state bits
        Info: Encoded state bit "estado.umcinquenta"
        Info: Encoded state bit "estado.um"
        Info: Encoded state bit "estado.cinquenta"
        Info: Encoded state bit "estado.zero"
    Info: State "|maquinaMercenaria|estado.zero" uses code string "0000"
    Info: State "|maquinaMercenaria|estado.cinquenta" uses code string "0011"
    Info: State "|maquinaMercenaria|estado.um" uses code string "0101"
    Info: State "|maquinaMercenaria|estado.umcinquenta" uses code string "1001"
Info: Implemented 13 device resources after synthesis - the final resource count might be different
    Info: Implemented 4 input pins
    Info: Implemented 1 output pins
    Info: Implemented 8 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings
    Info: Allocated 151 megabytes of memory during processing
    Info: Processing ended: Fri Sep 21 18:53:59 2007
    Info: Elapsed time: 00:00:04


