Classic Timing Analyzer report for maquinaMercenaria
Fri Sep 21 18:54:40 2007
Quartus II Version 7.1 Build 178 06/25/2007 Service Pack 1 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'clk'
  6. tsu
  7. tco
  8. th
  9. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                         ;
+------------------------------+-------+---------------+------------------------------------------------+--------------------+-------------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time                                    ; From               ; To          ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+--------------------+-------------+------------+----------+--------------+
; Worst-case tsu               ; N/A   ; None          ; 3.055 ns                                       ; moeda1             ; estado.um   ; --         ; clk      ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 6.707 ns                                       ; estado.umcinquenta ; refri       ; clk        ; --       ; 0            ;
; Worst-case th                ; N/A   ; None          ; -1.770 ns                                      ; moeda50            ; estado.zero ; --         ; clk      ; 0            ;
; Clock Setup: 'clk'           ; N/A   ; None          ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; estado.um          ; estado.um   ; clk        ; clk      ; 0            ;
; Total number of failed paths ;       ;               ;                                                ;                    ;             ;            ;          ; 0            ;
+------------------------------+-------+---------------+------------------------------------------------+--------------------+-------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1S10F484C5       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                                           ;
+-------+------------------------------------------------+--------------------+--------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From               ; To                 ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+--------------------+--------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; estado.um          ; estado.um          ; clk        ; clk      ; None                        ; None                      ; 1.349 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; estado.um          ; estado.umcinquenta ; clk        ; clk      ; None                        ; None                      ; 1.344 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; estado.cinquenta   ; estado.um          ; clk        ; clk      ; None                        ; None                      ; 1.279 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; estado.cinquenta   ; estado.umcinquenta ; clk        ; clk      ; None                        ; None                      ; 1.274 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; estado.zero        ; estado.um          ; clk        ; clk      ; None                        ; None                      ; 1.176 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; estado.zero        ; estado.umcinquenta ; clk        ; clk      ; None                        ; None                      ; 1.171 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; estado.umcinquenta ; estado.um          ; clk        ; clk      ; None                        ; None                      ; 1.159 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; estado.umcinquenta ; estado.umcinquenta ; clk        ; clk      ; None                        ; None                      ; 0.853 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; estado.cinquenta   ; estado.cinquenta   ; clk        ; clk      ; None                        ; None                      ; 0.847 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; estado.umcinquenta ; estado.zero        ; clk        ; clk      ; None                        ; None                      ; 0.743 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; estado.zero        ; estado.cinquenta   ; clk        ; clk      ; None                        ; None                      ; 0.660 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; estado.zero        ; estado.zero        ; clk        ; clk      ; None                        ; None                      ; 0.653 ns                ;
+-------+------------------------------------------------+--------------------+--------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-----------------------------------------------------------------------------+
; tsu                                                                         ;
+-------+--------------+------------+---------+--------------------+----------+
; Slack ; Required tsu ; Actual tsu ; From    ; To                 ; To Clock ;
+-------+--------------+------------+---------+--------------------+----------+
; N/A   ; None         ; 3.055 ns   ; moeda1  ; estado.um          ; clk      ;
; N/A   ; None         ; 3.050 ns   ; moeda1  ; estado.umcinquenta ; clk      ;
; N/A   ; None         ; 2.990 ns   ; moeda50 ; estado.um          ; clk      ;
; N/A   ; None         ; 2.985 ns   ; moeda50 ; estado.umcinquenta ; clk      ;
; N/A   ; None         ; 1.976 ns   ; moeda1  ; estado.cinquenta   ; clk      ;
; N/A   ; None         ; 1.972 ns   ; moeda1  ; estado.zero        ; clk      ;
; N/A   ; None         ; 1.886 ns   ; moeda50 ; estado.cinquenta   ; clk      ;
; N/A   ; None         ; 1.880 ns   ; moeda50 ; estado.zero        ; clk      ;
+-------+--------------+------------+---------+--------------------+----------+


+-----------------------------------------------------------------------------+
; tco                                                                         ;
+-------+--------------+------------+--------------------+-------+------------+
; Slack ; Required tco ; Actual tco ; From               ; To    ; From Clock ;
+-------+--------------+------------+--------------------+-------+------------+
; N/A   ; None         ; 6.707 ns   ; estado.umcinquenta ; refri ; clk        ;
+-------+--------------+------------+--------------------+-------+------------+


+-----------------------------------------------------------------------------------+
; th                                                                                ;
+---------------+-------------+-----------+---------+--------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From    ; To                 ; To Clock ;
+---------------+-------------+-----------+---------+--------------------+----------+
; N/A           ; None        ; -1.770 ns ; moeda50 ; estado.zero        ; clk      ;
; N/A           ; None        ; -1.776 ns ; moeda50 ; estado.cinquenta   ; clk      ;
; N/A           ; None        ; -1.862 ns ; moeda1  ; estado.zero        ; clk      ;
; N/A           ; None        ; -1.866 ns ; moeda1  ; estado.cinquenta   ; clk      ;
; N/A           ; None        ; -1.952 ns ; moeda1  ; estado.um          ; clk      ;
; N/A           ; None        ; -2.051 ns ; moeda1  ; estado.umcinquenta ; clk      ;
; N/A           ; None        ; -2.324 ns ; moeda50 ; estado.um          ; clk      ;
; N/A           ; None        ; -2.421 ns ; moeda50 ; estado.umcinquenta ; clk      ;
+---------------+-------------+-----------+---------+--------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.1 Build 178 06/25/2007 Service Pack 1 SJ Web Edition
    Info: Processing started: Fri Sep 21 18:54:39 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off maquinaMercenaria -c maquinaMercenaria --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 422.12 MHz between source register "estado.um" and destination register "estado.um"
    Info: fmax restricted to clock pin edge rate 2.369 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.349 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y1_N1; Fanout = 2; REG Node = 'estado.um'
            Info: 2: + IC(0.399 ns) + CELL(0.280 ns) = 0.679 ns; Loc. = LC_X1_Y1_N7; Fanout = 2; COMB Node = 'Selector2~330'
            Info: 3: + IC(0.351 ns) + CELL(0.319 ns) = 1.349 ns; Loc. = LC_X1_Y1_N1; Fanout = 2; REG Node = 'estado.um'
            Info: Total cell delay = 0.599 ns ( 44.40 % )
            Info: Total interconnect delay = 0.750 ns ( 55.60 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 3.009 ns
                Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 4; CLK Node = 'clk'
                Info: 2: + IC(1.639 ns) + CELL(0.542 ns) = 3.009 ns; Loc. = LC_X1_Y1_N1; Fanout = 2; REG Node = 'estado.um'
                Info: Total cell delay = 1.370 ns ( 45.53 % )
                Info: Total interconnect delay = 1.639 ns ( 54.47 % )
            Info: - Longest clock path from clock "clk" to source register is 3.009 ns
                Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 4; CLK Node = 'clk'
                Info: 2: + IC(1.639 ns) + CELL(0.542 ns) = 3.009 ns; Loc. = LC_X1_Y1_N1; Fanout = 2; REG Node = 'estado.um'
                Info: Total cell delay = 1.370 ns ( 45.53 % )
                Info: Total interconnect delay = 1.639 ns ( 54.47 % )
        Info: + Micro clock to output delay of source is 0.156 ns
        Info: + Micro setup delay of destination is 0.010 ns
Info: tsu for register "estado.um" (data pin = "moeda1", clock pin = "clk") is 3.055 ns
    Info: + Longest pin to register delay is 6.054 ns
        Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_U20; Fanout = 5; PIN Node = 'moeda1'
        Info: 2: + IC(3.181 ns) + CELL(0.280 ns) = 4.695 ns; Loc. = LC_X1_Y1_N2; Fanout = 1; COMB Node = 'Selector1~12'
        Info: 3: + IC(0.323 ns) + CELL(0.366 ns) = 5.384 ns; Loc. = LC_X1_Y1_N7; Fanout = 2; COMB Node = 'Selector2~330'
        Info: 4: + IC(0.351 ns) + CELL(0.319 ns) = 6.054 ns; Loc. = LC_X1_Y1_N1; Fanout = 2; REG Node = 'estado.um'
        Info: Total cell delay = 2.199 ns ( 36.32 % )
        Info: Total interconnect delay = 3.855 ns ( 63.68 % )
    Info: + Micro setup delay of destination is 0.010 ns
    Info: - Shortest clock path from clock "clk" to destination register is 3.009 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(1.639 ns) + CELL(0.542 ns) = 3.009 ns; Loc. = LC_X1_Y1_N1; Fanout = 2; REG Node = 'estado.um'
        Info: Total cell delay = 1.370 ns ( 45.53 % )
        Info: Total interconnect delay = 1.639 ns ( 54.47 % )
Info: tco from clock "clk" to destination pin "refri" through register "estado.umcinquenta" is 6.707 ns
    Info: + Longest clock path from clock "clk" to source register is 3.009 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(1.639 ns) + CELL(0.542 ns) = 3.009 ns; Loc. = LC_X1_Y1_N5; Fanout = 4; REG Node = 'estado.umcinquenta'
        Info: Total cell delay = 1.370 ns ( 45.53 % )
        Info: Total interconnect delay = 1.639 ns ( 54.47 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Longest register to pin delay is 3.542 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y1_N5; Fanout = 4; REG Node = 'estado.umcinquenta'
        Info: 2: + IC(1.138 ns) + CELL(2.404 ns) = 3.542 ns; Loc. = PIN_Y21; Fanout = 0; PIN Node = 'refri'
        Info: Total cell delay = 2.404 ns ( 67.87 % )
        Info: Total interconnect delay = 1.138 ns ( 32.13 % )
Info: th for register "estado.zero" (data pin = "moeda50", clock pin = "clk") is -1.770 ns
    Info: + Longest clock path from clock "clk" to destination register is 3.009 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(1.639 ns) + CELL(0.542 ns) = 3.009 ns; Loc. = LC_X1_Y1_N6; Fanout = 5; REG Node = 'estado.zero'
        Info: Total cell delay = 1.370 ns ( 45.53 % )
        Info: Total interconnect delay = 1.639 ns ( 54.47 % )
    Info: + Micro hold delay of destination is 0.100 ns
    Info: - Shortest pin to register delay is 4.879 ns
        Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_U19; Fanout = 5; PIN Node = 'moeda50'
        Info: 2: + IC(3.187 ns) + CELL(0.458 ns) = 4.879 ns; Loc. = LC_X1_Y1_N6; Fanout = 5; REG Node = 'estado.zero'
        Info: Total cell delay = 1.692 ns ( 34.68 % )
        Info: Total interconnect delay = 3.187 ns ( 65.32 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 106 megabytes of memory during processing
    Info: Processing ended: Fri Sep 21 18:54:40 2007
    Info: Elapsed time: 00:00:01


