---------------------------------------------------------------------------------- -- Company: LISHA - Laboratory for Software/Hardware Integration - Federal University of Santa Catarina -- Engineer: João Paulo Pizani Flor, B.Sc -- -- Create Date: 18:32:25 02/09/2011 -- Design Name: -- Module Name: spartan3_picoblaze -- Project Name: -- Target Devices: -- Tool versions: -- Description: "Glue" logic for integrating a picoblaze core (with rom), -- push buttons and 7-segment displays. Originally made for the Spartan3 -- evaluation board, but can be used for other FPGAs and kits also. -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity Spartan3PicoBlaze is Port ( mclk : in std_logic; btn : in std_logic_vector(3 downto 0); swt : in std_logic_vector(7 downto 0); led : out std_logic_vector(7 downto 0); an : out std_logic_vector(3 downto 0); low_7segs : out std_logic_vector(7 downto 0)); end Spartan3PicoBlaze; architecture Behavioral of Spartan3PicoBlaze is ------------------------------------------------------------------------ -- Components ------------------------------------------------------------------------ component embedded_kcpsm is Port ( port_id : out std_logic_vector(7 downto 0); write_strobe : out std_logic; read_strobe : out std_logic; out_port : out std_logic_vector(7 downto 0); in_port : in std_logic_vector(7 downto 0); interrupt : in std_logic; reset : in std_logic; clk : in std_logic); end component; component ssd_displaydriver_4digits is Port( clk, reset : in std_logic; char0, char1, char2, char3 : in std_logic_vector(3 downto 0); ssg : out std_logic_vector(7 downto 0); an : out std_logic_vector(3 downto 0)); end component; ------------------------------------------------------------------------ -- Signals ------------------------------------------------------------------------ signal clkdiv : std_logic_vector(23 downto 0); signal cntr : std_logic_vector(3 downto 0); signal cclk : std_logic; signal slowclk : std_logic; signal hi_7segs : std_logic_vector(7 downto 0); signal port_id : std_logic_vector(7 downto 0); signal write_strobe : std_logic; signal out_port : std_logic_vector(7 downto 0); signal read_strobe : std_logic; signal in_port : std_logic_vector(7 downto 0); signal interrupt : std_logic; signal reset : std_logic; signal dig0, dig1, dig2, dig3 : std_logic_vector(3 downto 0); begin ------------------------------------------------------------------------ -- Module Implementation ------------------------------------------------------------------------ processor: embedded_kcpsm port map( port_id => port_id, write_strobe => write_strobe, out_port => out_port, read_strobe => read_strobe, in_port => in_port, interrupt => interrupt, reset => reset, clk => cclk); display_driver: ssd_displaydriver_4digits port map( clk => mclk, reset => reset, char0 => dig0, char1 => dig1, char2 => dig2, char3 => dig3, ssg => hi_7segs, an => an); input_ports: process(cclk) begin if rising_edge(cclk) then case port_id is when "00000000" => in_port <= swt; when "11111111" => in_port <= ext(btn,8); when others => null; end case; end if; end process input_ports; output_ports: process(cclk) begin if rising_edge(cclk) then if write_strobe='1' then case port_id is when "00000000" => dig0 <= out_port(3 downto 0); when "00000001" => dig1 <= out_port(3 downto 0); when "00000010" => dig2 <= out_port(3 downto 0); when "00000011" => dig3 <= out_port(3 downto 0); when "10100000" => led <= out_port; when others => null; end case; end if; end if; end process output_ports; interrupt_pulse: process (slowclk) variable state : boolean := false; begin if rising_edge(slowclk) then if (btn(0)='1' or btn(1)='1' or btn(2)='1') and (not state) then interrupt <= '1'; state := true; elsif (btn(0)='1' or btn(1)='1' or btn(2)='1') and state then interrupt <= '0'; else state := false; end if; end if; end process; clock_divisor: process (mclk) begin if rising_edge(mclk) then clkdiv <= clkdiv + 1; end if; end process; low_7segs <= not hi_7segs; cclk <= clkdiv(14); slowclk <= clkdiv(16); end Behavioral;